A low voltage, low power, UWB down-converter on 0.18-μm RF silicon CMOS

This paper presents the results of an UWB down-converter mixer design that works with a 0.7V VDD supply, consumes 0.71mW power, and achieves 3-dB bandwidth of 0.6 to 11GHz.

Characteristic Impedance

This document shares a conceptual insight on the characteristic impedance topic. Last night, I was thinking about a method to explain (in simple words) "characteristic impedance". More particularly, explaining how the characteristic impedance is different than the conventional concept of the impedance. My conclusion was that the best viewpoint to the concept of characteristic impedance is the one that looking through the signal time window, (i.e. traveling / propagating with the signal peak through the circuit). This document, actually, employs a similar method.

Special Matrices

Matrix Reference Manual includes a short description about special matrices and their properties. Absolutely useful. I was looking for a matrix with the following form:

A = [ 1 0 ...   0

      1 1 0 ... 0

      0 1 1 ... 0

      :

      0 ...   1 1

      0 ...   0 1]

Referring to special matrices page, I found out that A can be a Toeplitz matrix for which a_ij = a0 where i=j; otherwise a_(i+1)(j+1) = a_ij, (i.e. a_ij only depends on i-j).

A PLL tutorial

This tutorial presents an engineering overview of Phase Locked Loop design. I am particularly interested in  "Digital PLL" (slide 91). The pros and cons of Digital PLLs are listed as follows:

Why a Digital PLL?

• Replaces process and noise-sensitive analog circuits with digital equivalents – advances on work with digital DLLs;
• Increases PLL design portability and testability;
• Takes advantage of area scaling with nm devices;
• Greater flexibility in loop bandwidth – don‟t need huge capacitors for low BW;
• Increases ability to test and observe. e.g. open-loop, disturb loop;
• Fast behavioral simulation;
• “Good-enough” for frequency synthesis applications;
• ISSCC presentations: TI('04) and IBM ('07).

Why NOT a Digital PLL?

• Often not “good enough” for phase-tracking applications;
• VCO frequency has finite frequency resolution (e.g. 10-14 bits). May use coarse DAC if high-frequency dithering available;
• VCO has limited range – requires range control and/or calibration;
• VCO may have poor noise rejection if purely digital frequency control and no voltage regulator (usually analog);
• Need high-frequency over-sampling clock for sigma-delta loop filter – VCO? Refclk? Start-up problem?;
• TimeError-to-Digital Converter is hard – poor resolution, high power – usually < 5 bits;
• Bang-bang is an alternative (IBM);
• FbDiv internal state contains phase error information.
• Digital filter generates large noise spurs, possibly inducing jitter, and dissipates more power than passive loop filter;
• Requires delta-sigma modulation to reduce spurs.
• Generating proportional correction can be tricky.

NGSPICE / gEDA startup

I have installed ngspice simulator and gEDA products over a CentOS5.8 virtual machine. I had problems installing it over debian and FreeBSD but CentOS is good so far.

I can draw the schematic of the circuits in gschem (schematic drawer of gEDA) and make a netlist from the given schem for importing into ngspice. The only trick is to assign reasonable netlist name, refdes, and value to each component in the schematic.  Here is a good tutorial that helped me to setup my first test.

The following includes my test2.cir based on the given example at this link:

1- The schematic is available here. This file can be opened by gschem platform. Please notice to "netlist name, refdes, and value" parameters for each component.

2-now it is time to convert the schematic file to a netlist for spice simulator. We can easily do this by running "gnetlis" command of gEDA:
       [xx@localhost yy]$ gnetlist -g spice -o test2.cir test2.sch

3- run ngspice simulator:
        [xx@localhost yy]$ ngspice

4- source test2.cir
        ngspice 1 -> source test2.cir

5- for AC frequency analysis with linear scaling, step size of 1000Hz, over 0.1Hz-250KHz frequency band (more details are available here):
        ngspice 2 -> ac lin 1000 0.1 250KHz

6- there are two nodes indicated by n1 and n2 in the schematic. We can plot the voltage of these nodes over the above mentioned frequency range:
        ngspice 3 -> plot v(n2)

Circuit vs. Device level Simulator

Here is a nice review comparing a circuit level simulator, (e.g. NGSPICE), versus a device simulator, (e.g. General purpose Semiconductor Simulator). It also describes how users can integrate GSS in NGSPICE. I would like to share the following figure from the document that clarifies the difference from a high-level perspective.

  

3PGCIC presentation

The presentation slides are available here. The full paper can be find at this link.

Frequency Dividers

"Frequency Divider Design for Mlti-GHz PLL Systems" is the title of a dissertation by "Francesco Barale" that sufficiently reviews various frequency dividers used in a PLL loop. The dissertation compares programmable divider (a digital counter) with analog divider solutions (master-slave latch divider, MS divider, and injection-locking divider, ILD). It concludes that for multi-GHz PLLs, analog dividers should be used in the first stages of the clock dividing branch, as show below:

Fig. 6 on page 11: It is recommended that ILD comes at the very first stage ("The ILD solution allows the highest frequency of operation but, in general, offers a narrower bandwidth and higher power consumption when compared with the MS solution").