"Frequency Divider Design for Mlti-GHz PLL Systems" is the title of a dissertation by "Francesco Barale" that sufficiently reviews various frequency dividers used in a PLL loop. The dissertation compares programmable divider (a digital counter) with analog divider solutions (master-slave latch divider, MS divider, and injection-locking divider, ILD). It concludes that for multi-GHz PLLs, analog dividers should be used in the first stages of the clock dividing branch, as show below:
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| Fig. 6 on page 11: It is recommended that ILD comes at the very first stage ("The ILD solution allows the highest frequency of operation but, in general, offers a narrower bandwidth and higher power consumption when compared with the MS solution"). |
