mos capacitor

reference book chapter

three region of operations:
- accumulation
- depletion
-inversion

in inversion we need S/D N donors to be the bottom plate of Cox cap (create a relatively low impedance path). The following curve show the gate cap in different regions.

slicide vs. non-silicide resistors

high resistance resistors: non-silicide

poly resistors: slicide-block mask should be used

poly gate contacts: silicide to enhance speed 

silicon on insulator CMOS

the picture speaks about the difference in topology of the device. The device at the top is a normal CMOS that the diffusion is implanted in the substrate but the one at the bottom, the substrate is insulated with an oxide region from the part of silicon that would construct the device channel. The benefits are: lower leakage, lower substrate noise to the channel, no body connection is required, device can operate lower than VDD, etc.

CMOS chopper amplifier to reduce 1/f noise

The paper reviews CMOS chopper amplifier theory and actual circuit. The theory is simple: modulate the input signal to F_chopper where 1/f noise is not significant, amplify the modulated signal. and finally demodulate and reconstruct low pass signal at the output. Also, found this work interesting: using CMOS devices in lateral bipolar mode to decrease 1/f noise (see figure 14).

Noise Sources in Bulk CMOS

A nice summary on CMOS noise sources(flicker, shot, thermal).

Random DC Offset of Comparators

These slides review Flash ADC circuits. The source of random DC offset is the random fabrication mismatch. The reference paper, "Matching Properties of CMOS Transistors" (1989) divides the mismatch to two models: local and global.

Charge Injection in CMOS switches

"Charge Injection in Analog CMOS Switches" (1987) presents a model for charge injection. It also proposes some methods to alleviate charge injection by design.

Serial Charge Redistribution DAC

The slides introduce ABC of charge redistribution DAC.

CMOS Capacitance and Delay

handy notes on CMOS delay. Analyse the capacitance and connect it to delay of circuits (driver load and total load capacitance).

Gilbert Mixer: Secod order order (IM2/HD2) nonlinearities

In one of our tests, we noticed a significant HD2 at the output of a differential passive Gilbert cell mixer (the mixer performance was supposed to be at least 20dB better than what we measured in the lab). I was looking for a systematic methodology to link this problem to load mismatches on P and N paths. In my research, I came across this paper [this webpage includes better quality images] that categorizes second order nonlinearities of a Gilbert cell. My take on this work is Eq. (16), where the IM2 output voltage is extracted by i_im2_diff (differential current IM2) and i_im2_cm (common mode current IM2). The equation express the relation between the overall IM2 and internally+externally generated IM2. In other words, if the output load is matched (load of path N and P are equal in terms of phase and amplitude) then i_im2_cm's impact will be canceled by teh balance between the loads (P&N) , i.e. delta_Rload*i_im2_cm becomes almost 0. On the other hand, i_im2_diff (generated by internal transconductance/timing mismatches) will be signified by sum_Rload (Rload_P+R_load_N). In my case, I guessed that the strong HD2 would have been generated by P&N load mismatched; however, later we found out that the input signal to the mixer was imbalance!!!

A low voltage, low power, UWB down-converter on 0.18-μm RF silicon CMOS

This paper presents the results of an UWB down-converter mixer design that works with a 0.7V VDD supply, consumes 0.71mW power, and achieves 3-dB bandwidth of 0.6 to 11GHz.