Showing posts with label PLL. Show all posts
Showing posts with label PLL. Show all posts

Wednesday, January 17, 2018

PFD switching impact on charge pump noise

we are intersted to calculate input reffered phase noise of charge pump when reference clock is f1 and 2xf1. More particularly, we want to know how increasing reference frequency would impact input reffered noise of PFD-CP cascaded circuits. Lets assume that charge pump is a a current source that has a frequency domain response. It is fair to assume charge pump single ended noise spectrum to be:


 Sx(f)
  |
  |
  |\
  | \
  |  \ 1/f
  |   \
  |    \
  |     \__________
  |     .
  |_____.______________ freq.
        fc
it has a flicker corner at $f_c$. we now assume that a noise profile with power spectral density of Sx(f) is injected to an LTI system, H(f), that represent the switching behavior of PFD when PLL is in lock condition.

 
h(t)
  | 
A |   __Tp___        _______        _______
  |   |     |        |     |        |     |
  |___|     |________|     |________|     |________
      ........Ts......

\begin{eqnarray}

H \left( f \right) &=& 2 \pi \Sigma_{n=-\infty}^{+\infty} \left( \frac{T_p}{T_s} sinc\left( \frac{n T_p}{T_s} \right) \right) \delta \left( f-n f_s \right) \\

&=& 2 \pi \Sigma_{n=-\infty}^{+\infty} \left( T_p f_s sinc\left( n T_p f_s \right) \right) \delta \left( f-n f_s \right)

\end{eqnarray}



the power spectral density of $S_x(f)$ noise after filtering by $H(f)$ is

\begin{eqnarray}
S_y \left( f \right) &=& \left| H \left( f \right) \right|^2 S_x \left( f \right)
\end{eqnarray}


$S_y \left( f \right) $ is increasing 6dB for 2x increase of $f_s$ frequency (because of $\left| H \left( f \right) \right|^2$ factor).

now we need to analyse the impact of folding (PFD switching) on the spectrum, i.e.  $\Sigma_{n=-\infty}^{+\infty} \left(. \right)$. In reality, charge pump bandwidth is limited and the spectrum is as shown below:


 Sx(f)
  |
  |
  |\
  | \
  |  \ 1/f
  |   \
  |    \
  |     \__________
  |      .         |
  |______._________|_________ freq.
         fc        f0

$f_c$ is flicker corner, and $f_0$ is the bandwidth of analog charge pump. We also assume that $f_0 >> f_s$ and $f_c << f_s$. The key to noise folding analysis is that the tail of $S_x(f)$ noise is thermal and has much less power than the flicker region.

* Thermal noise region ($f>f_c$) folded in flicker region, $f < f_c $, [lets only talk about noise folding in the first Nyquist zone], has almost zero impact on the power of noise in flicker region.

** Thermal noise region ($f>f_c$) folded in thermal noise region increase the noise floor because the power of folding term is comparable to the power of the thermal noise.

the question is: "what is the impact of refrence frequency ($f_s$) on different noise regions?"

by increasing $f_s$, $K$ will be reduced. It means that for larger reference frequency, we have less folding terms in noise thermal region. flicker region doesn't change (significantly) by noise folding mechanism becuase flicker noise power is much higher than thermal noise that is folding in flicker region. For example, if $f_s$ is increased by 2x, output reffered flicker noise increasing by 6dB (as $|H(f)|.^2$ gain does); however, thermal noise region increased by +6dB-3dB (6dB follows $|H(f)|.^2$ gain increase and -3dB is because, increasing $f_s$ introduces 2x less folding terms in thermal region).

Summary: refrence frequency ($f_s$) has the superposition of the following impacts on charge pump output refered phase noise:

1) increasing refernce frequency from $f_{s1}$ to $f_{s2}$, increases the whole CP output reffered noise by $20 \log_{10} \left(\frac{f_{s2}}{f_{s1}} \right)$
2) increasing refernce frequency from $f_{s1}$ to $f_{s2}$, decreases thermal noise of CP by $-10 \log_{10} \left(\frac{f_{s2}}{f_{s1}} \right)$ but doesn't change the flicker noise





Wednesday, January 3, 2018

PLL type-II Nyquist stability


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% analyse Nyquist stability criteria for PLL-type II

function [RE,IM,W]=pll_typeII_nyquist_stab(Icp,kvco,pm,bw,N)
% Icp: charge pump current [A]
% kvco: VCO gain [Hz/V]
% pm: phase margin [deg]
% bw: 3dB closed loop bandwidth [Hz] 
% N: feeback divider ratio

[R1,C1,C2]=pll_typeII_get_loop_filter (Icp,kvco,pm,bw,N); % get loop filter components
z1=1/R1/C1;
p1=(C1+C2)/C1/C2/R1;

% open loop transfer function A(s)=Icp*kvco*Z(s)/s/N = Icp*kvco/C2/N/s^2*(s+z1)/(s+p1)

num=Icp*kvco/C2/N*[1 z1];
den=[1 p1 0 0];
s1=tf(num,den);

wi=logspace(5.5,8,10000);
[RE,IM,W] = nyquist(s1,wi);
phi=atan2(IM(1),RE(1));
z=sqrt(RE(1)^2+IM(1)^2)*exp(j*[phi:-phi/100:-phi]);
figure
plot(RE,IM,'-b','linewidth',2);
hold on;
plot(RE,-IM,'-r','linewidth',2);
plot(real(z),imag(z),'--k','linewidth',1);
plot(-1,0,'xm','markers',12,'linewidth',3);
plot(-1+cos(pi/180*[0:4:360]),sin(pi/180*[0:4:360]),'-.k','linewidth',2);
grid on;
legend({"+w","-w","contour","-1+j0"})
title(['Nyquist plot'],'fontsize',18);
ylabel('IMG','fontsize',16);
xlabel('RE','fontsize',16);
maxR=max(sqrt(RE.^2+IM.^2))+1;
axis([-maxR maxR -maxR maxR],"square"); 
set(gca,'fontsize',14,'xtick',[-maxR,-1,0,maxR],'xticklabel',{'-\infty','-1','0','+\infty'},'ytick',[-maxR,0,maxR],'yticklabel',{'-\infty','0','+\infty'});

saveas(gcf,'figures/nyquist_stability.png','png')

2nd order-typ2-II PLL loop filter analysis


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% design a loop filter for a typeII PLL
% the folrmulas are based on this analysis: http://sss-mag.com/pdf/pllfil.pdf
%
%           Icp_\___________________________Vctrl 
%               /     |                 |
%                     \                 | 
%                     /  R1 ohms        |
%                     \                 |
%                     /                 |
%                     |                _|_
%                    _|_               ___ C2 F
%                    ___ C1 F           |
%                     |                 |
%                    _|_               _|_
%                    \ /               \ /
%
%


function [R1,C1,C2]=pll_typeII_get_loop_filter (Icp,kvco,pm,bw,N)
% Icp: charge pump current [A]
% kvco: VCO gain [Hz/V]
% pm: phase margin [deg]
% bw: 3dB closed loop bandwidth [Hz] 
% N: feeback divider ratio 

% Z(s): impedance of loop filter
% Z(s) = (s+1/R1/C1)/(C2*s*(s+(C1+C2)/C1/C2/R1))
% z1=1/R1/C1
% p1=(C1+C2)/C1/C2/R1
% Z(s) = (s+z1)/C2/s/(s+p1)

% A(s): open loop transfer function

% ----------        |\
% | phi_in |--------|+\         __________          ________       ____________
% ----------        |  \________|Icp/2/pi|__________| Z(s) |_______|2*pi*kvco/s|______________phi_out
%                   |  /        ---------           -------        ------------  |
%               ----|-/                                                          |
%               |   |/                                              -----        |
%               |___________________________________________________| %N |_______|
%                                                                   -----
%
%  A(s) = Icp*kvco*Z(s)/s/N = Icp*kvco/C2/N/s^2*(s+z1)/(s+p1)
%  phase[A(s=jw)]=-180+arctan(w/z1)-arctan(w/p1)
%  PM: phase margin
%  PM = arctan(w/z1)-arctan(w/p1) = arctan[(p1-z1)*w/(w^2+p1*z1)]
%  design loop filter to maximize PM: d[(p1-z1)*w/(w^2+p1*z1)]/dw=0 --> wp=sqrt(p1*z1)
%  by PM definition we have: |A(s=jwp)|=1
%  closed loop transfer function: T(s) 
%  (phi_in-phi_out/N)*[A(s)*N] = phi_out --> T(s) = phi_out/phi_in = N*A(s)/(1+A(s))
%  3dB bandwidth, w0=2*pi*bw, is achived when |T(s=jw0)| = N/2; this can be achived for A(s=jw0) = j
%  we know that at wp, |A(s=jwp)|=1 and by maximizing PM at wp, we can assume that w0 is approximately equal to wp
%  using trigonometry equality of sec(tetha)=sqrt(1+tan^2(tetha)): z1=wp*(sec(PM)-tan(PM))
wp = 2*pi*bw;
tetha = pm*pi/180;
z1 = wp*(sec(tetha)-tan(tetha));
p1 = wp^2/z1;
C2= Icp*kvco/N/wp^2*sqrt(wp^2+z1^2)/sqrt(wp^2+p1^2); % using |A(s=jwp)|=1
C1=(p1/z1-1)*C2;
R1=1/C1/z1;

Saturday, November 1, 2014

Friday, January 11, 2013

A PLL tutorial

This tutorial presents an engineering overview of Phase Locked Loop design. I am particularly interested in  "Digital PLL" (slide 91). The pros and cons of Digital PLLs are listed as follows:

Why a Digital PLL?
  • Replaces process and noise-sensitive analog circuits with digital equivalents – advances on work with digital DLLs;
  • Increases PLL design portability and testability;
  • Takes advantage of area scaling with nm devices;
  • Greater flexibility in loop bandwidth – don‟t need huge capacitors for low BW;
  • Increases ability to test and observe. e.g. open-loop, disturb loop;
  • Fast behavioral simulation;
  • “Good-enough” for frequency synthesis applications;
  • ISSCC presentations: TI('04) and IBM ('07).
Why NOT a Digital PLL?
  • Often not “good enough” for phase-tracking applications;
  • VCO frequency has finite frequency resolution (e.g. 10-14 bits). May use coarse DAC if high-frequency dithering available;
  • VCO has limited range – requires range control and/or calibration;
  • VCO may have poor noise rejection if purely digital frequency control and no voltage regulator (usually analog);
  • Need high-frequency over-sampling clock for sigma-delta loop filter – VCO? Refclk? Start-up problem?;
  • TimeError-to-Digital Converter is hard – poor resolution, high power – usually < 5 bits;
    • Bang-bang is an alternative (IBM);
    • FbDiv internal state contains phase error information.
  • Digital filter generates large noise spurs, possibly inducing jitter, and dissipates more power than passive loop filter;
    • Requires delta-sigma modulation to reduce spurs.
  • Generating proportional correction can be tricky.