Gilbert Mixer: Secod order order (IM2/HD2) nonlinearities

In one of our tests, we noticed a significant HD2 at the output of a differential passive Gilbert cell mixer (the mixer performance was supposed to be at least 20dB better than what we measured in the lab). I was looking for a systematic methodology to link this problem to load mismatches on P and N paths. In my research, I came across this paper [this webpage includes better quality images] that categorizes second order nonlinearities of a Gilbert cell. My take on this work is Eq. (16), where the IM2 output voltage is extracted by i_im2_diff (differential current IM2) and i_im2_cm (common mode current IM2). The equation express the relation between the overall IM2 and internally+externally generated IM2. In other words, if the output load is matched (load of path N and P are equal in terms of phase and amplitude) then i_im2_cm's impact will be canceled by teh balance between the loads (P&N) , i.e. delta_Rload*i_im2_cm becomes almost 0. On the other hand, i_im2_diff (generated by internal transconductance/timing mismatches) will be signified by sum_Rload (Rload_P+R_load_N). In my case, I guessed that the strong HD2 would have been generated by P&N load mismatched; however, later we found out that the input signal to the mixer was imbalance!!!

Characteristic Impedance

This document shares a conceptual insight on the characteristic impedance topic. Last night, I was thinking about a method to explain (in simple words) "characteristic impedance". More particularly, explaining how the characteristic impedance is different than the conventional concept of the impedance. My conclusion was that the best viewpoint to the concept of characteristic impedance is the one that looking through the signal time window, (i.e. traveling / propagating with the signal peak through the circuit). This document, actually, employs a similar method.

Frequency Dividers

"Frequency Divider Design for Mlti-GHz PLL Systems" is the title of a dissertation by "Francesco Barale" that sufficiently reviews various frequency dividers used in a PLL loop. The dissertation compares programmable divider (a digital counter) with analog divider solutions (master-slave latch divider, MS divider, and injection-locking divider, ILD). It concludes that for multi-GHz PLLs, analog dividers should be used in the first stages of the clock dividing branch, as show below:

Fig. 6 on page 11: It is recommended that ILD comes at the very first stage ("The ILD solution allows the highest frequency of operation but, in general, offers a narrower bandwidth and higher power consumption when compared with the MS solution").