silicon on insulator CMOS

the picture speaks about the difference in topology of the device. The device at the top is a normal CMOS that the diffusion is implanted in the substrate but the one at the bottom, the substrate is insulated with an oxide region from the part of silicon that would construct the device channel. The benefits are: lower leakage, lower substrate noise to the channel, no body connection is required, device can operate lower than VDD, etc.

Logical Effort: design logics in CMOS

so far found the following chapters of "Logical Efforts" by Sutherland, Sproull, and Harris:
Chapter 1: The Method of Logical Effort
Chapter 4: Calculating the Logical Effort of Gates
Chapter 10: Circuit Families

and this presentation slide by Harris.