A PLL tutorial

This tutorial presents an engineering overview of Phase Locked Loop design. I am particularly interested in  "Digital PLL" (slide 91). The pros and cons of Digital PLLs are listed as follows:

Why a Digital PLL?

• Replaces process and noise-sensitive analog circuits with digital equivalents – advances on work with digital DLLs;
• Increases PLL design portability and testability;
• Takes advantage of area scaling with nm devices;
• Greater flexibility in loop bandwidth – don‟t need huge capacitors for low BW;
• Increases ability to test and observe. e.g. open-loop, disturb loop;
• Fast behavioral simulation;
• “Good-enough” for frequency synthesis applications;
• ISSCC presentations: TI('04) and IBM ('07).

Why NOT a Digital PLL?

• Often not “good enough” for phase-tracking applications;
• VCO frequency has finite frequency resolution (e.g. 10-14 bits). May use coarse DAC if high-frequency dithering available;
• VCO has limited range – requires range control and/or calibration;
• VCO may have poor noise rejection if purely digital frequency control and no voltage regulator (usually analog);
• Need high-frequency over-sampling clock for sigma-delta loop filter – VCO? Refclk? Start-up problem?;
• TimeError-to-Digital Converter is hard – poor resolution, high power – usually < 5 bits;
• Bang-bang is an alternative (IBM);
• FbDiv internal state contains phase error information.
• Digital filter generates large noise spurs, possibly inducing jitter, and dissipates more power than passive loop filter;
• Requires delta-sigma modulation to reduce spurs.
• Generating proportional correction can be tricky.