Showing posts with label CML. Show all posts
Showing posts with label CML. Show all posts

Wednesday, March 30, 2016

Current Mode Logic Active Inductor Load

Active inductor load can be designed by applying a negative voltage feedback from drain of an active current load to the gate of the active load. The feedback has a time constant that depends on the size of gate resistor and Cgs of the active load. Overall, feedback makes the load to behave like an inductor where $L=\frac{R_g C_{gs}}{g_m}$. For more details refer to page 68 of this Master's thesis. The following image is also captured from the thesis.