Random DC Offset of Comparators

These slides review Flash ADC circuits. The source of random DC offset is the random fabrication mismatch. The reference paper, "Matching Properties of CMOS Transistors" (1989) divides the mismatch to two models: local and global.

Charge Injection in CMOS switches

"Charge Injection in Analog CMOS Switches" (1987) presents a model for charge injection. It also proposes some methods to alleviate charge injection by design.

Serial Charge Redistribution DAC

The slides introduce ABC of charge redistribution DAC.

Fractional Frequency Divider by Delta-Sigma Modulator

"Delta-sigma modulation in fractional-N frequency synthesis" (1993) compares pulse swallowing, phase interpolation, and Wheatley random jittering methods with Delta-Sigma jittering technique.

CMOS Capacitance and Delay

handy notes on CMOS delay. Analyse the capacitance and connect it to delay of circuits (driver load and total load capacitance).

PLL close loop bandwidth

The slides cover PLL analysis from a system point of view.

A tutorial on Phase Locked Loops

This tutorial is recommended by a senior member of my team: "Design of Monolithic Phase Locked Loops and Clock Recovery Circuits: A Tutorial".

Are uncorrelated normal random variables necessarily independent?

Professor Rosenthal nicely explained this questions by giving two clear examples. The golden quote is "What is true is that if the random variable pair (X,Y) follows the bivariate normal distribution, and Cov(X,Y) = 0, then X and Y must be independent. But what is not true is that if each of X and Y is normally distributed, and Cov(X,Y) = 0, then X and Y must be independent".

An Overview of Boundary Scan Test Methodology

An abstract review of boundary scan test methodology is available here. Pros and cons are introduced as below:

Benefits:

• Reusable Test Vectors
• Reduced Test Time
• Reduced Time to Market
• Faster ROI
• Reduced Design Iterations
• Efficient and Economical Production
• Functional Test

Challenges:

• Area Overhead / Additional Circuits
• Additional Pins
• Higher Design Effort
• Performance Degradation
• Power Consumption

Digital Signatures Verification

Heartbleed bug and stories around it motivated me to review the SSL security. Here is a good review of Digital Signature. It provides graphical flow charts of the procedure that eases the review ....

Multivariate Mutual Information

Here is a useful review on "Multivariate Mutual Information". I'm working on the negative interaction in a tri-variate problem. The definition of semi-independent distribution caught my attraction. From [Han'80: Multiple Mutual Informations and Multiple Interactions in Frequency Data], a tri-variate distribution (U,V,Y) is semi-independent if

Pr{U V Y} = Pr{U} Pr{V Y} + Pr{V} Pr{U Y} + Pr{Y} P r{U V} − 2 Pr{U} Pr{V} Pr{Y}

DFT and windowing

Recently, I was working on a feasibility study of measuring/detecting IM3s of an ADC output by capturing only 512 samples, where the sampling rate is about 300MS/sec. During this research, I came across "On the Use of Windows for Harmonic Analysis with the Discrete Fourier Transform", by F. Harris (1978). This paper is a must-read for signal processing folks.
The concepts such as spectral resolution, the window processing loss (gain), 6-dB BW of the window, etc. need to be considered in any DFT design/analysis. As the figure below, with 512 samples, the signal intermods are not detectable if we do not use a proper window.

 

Gilbert Mixer: Secod order order (IM2/HD2) nonlinearities

In one of our tests, we noticed a significant HD2 at the output of a differential passive Gilbert cell mixer (the mixer performance was supposed to be at least 20dB better than what we measured in the lab). I was looking for a systematic methodology to link this problem to load mismatches on P and N paths. In my research, I came across this paper [this webpage includes better quality images] that categorizes second order nonlinearities of a Gilbert cell. My take on this work is Eq. (16), where the IM2 output voltage is extracted by i_im2_diff (differential current IM2) and i_im2_cm (common mode current IM2). The equation express the relation between the overall IM2 and internally+externally generated IM2. In other words, if the output load is matched (load of path N and P are equal in terms of phase and amplitude) then i_im2_cm's impact will be canceled by teh balance between the loads (P&N) , i.e. delta_Rload*i_im2_cm becomes almost 0. On the other hand, i_im2_diff (generated by internal transconductance/timing mismatches) will be signified by sum_Rload (Rload_P+R_load_N). In my case, I guessed that the strong HD2 would have been generated by P&N load mismatched; however, later we found out that the input signal to the mixer was imbalance!!!

LNA linearization methods

This presentation reviews the analog techniques to linearize LNAs.

On oversampling of quantization noise

This is about Eq.(3) of [Candy'92]. Basically, I keep asking myself why the sampled quantized noise spectral density is given by


where the quantization noise is a white process with the following RMS value:


[Candy'92] explains that due to sampling, the noise power folds into the frequency band

However, I have to find a self-convincing explanation.

Here is how I understand the impact of oversampling on quantization noise:

1- we should consider a LPF with the bandwidth of

2- the sampling/quantization system is as follows [x denotes the instantaneous quantization noise]:

x--|sampler|--|LPF: h[n]|--y



3- Auto-covariance of LPF output is given by:


4- for a ideal LPF with f_0 = f_s/2, we have



5- Consequently the density of the quantization noise, which spreads over

is given by

A low voltage, low power, UWB down-converter on 0.18-μm RF silicon CMOS

This paper presents the results of an UWB down-converter mixer design that works with a 0.7V VDD supply, consumes 0.71mW power, and achieves 3-dB bandwidth of 0.6 to 11GHz.

Characteristic Impedance

This document shares a conceptual insight on the characteristic impedance topic. Last night, I was thinking about a method to explain (in simple words) "characteristic impedance". More particularly, explaining how the characteristic impedance is different than the conventional concept of the impedance. My conclusion was that the best viewpoint to the concept of characteristic impedance is the one that looking through the signal time window, (i.e. traveling / propagating with the signal peak through the circuit). This document, actually, employs a similar method.

Special Matrices

Matrix Reference Manual includes a short description about special matrices and their properties. Absolutely useful. I was looking for a matrix with the following form:

A = [ 1 0 ...   0

      1 1 0 ... 0

      0 1 1 ... 0

      :

      0 ...   1 1

      0 ...   0 1]

Referring to special matrices page, I found out that A can be a Toeplitz matrix for which a_ij = a0 where i=j; otherwise a_(i+1)(j+1) = a_ij, (i.e. a_ij only depends on i-j).

A PLL tutorial

This tutorial presents an engineering overview of Phase Locked Loop design. I am particularly interested in  "Digital PLL" (slide 91). The pros and cons of Digital PLLs are listed as follows:

Why a Digital PLL?

• Replaces process and noise-sensitive analog circuits with digital equivalents – advances on work with digital DLLs;
• Increases PLL design portability and testability;
• Takes advantage of area scaling with nm devices;
• Greater flexibility in loop bandwidth – don‟t need huge capacitors for low BW;
• Increases ability to test and observe. e.g. open-loop, disturb loop;
• Fast behavioral simulation;
• “Good-enough” for frequency synthesis applications;
• ISSCC presentations: TI('04) and IBM ('07).

Why NOT a Digital PLL?

• Often not “good enough” for phase-tracking applications;
• VCO frequency has finite frequency resolution (e.g. 10-14 bits). May use coarse DAC if high-frequency dithering available;
• VCO has limited range – requires range control and/or calibration;
• VCO may have poor noise rejection if purely digital frequency control and no voltage regulator (usually analog);
• Need high-frequency over-sampling clock for sigma-delta loop filter – VCO? Refclk? Start-up problem?;
• TimeError-to-Digital Converter is hard – poor resolution, high power – usually < 5 bits;
• Bang-bang is an alternative (IBM);
• FbDiv internal state contains phase error information.
• Digital filter generates large noise spurs, possibly inducing jitter, and dissipates more power than passive loop filter;
• Requires delta-sigma modulation to reduce spurs.
• Generating proportional correction can be tricky.

NGSPICE / gEDA startup

I have installed ngspice simulator and gEDA products over a CentOS5.8 virtual machine. I had problems installing it over debian and FreeBSD but CentOS is good so far.

I can draw the schematic of the circuits in gschem (schematic drawer of gEDA) and make a netlist from the given schem for importing into ngspice. The only trick is to assign reasonable netlist name, refdes, and value to each component in the schematic.  Here is a good tutorial that helped me to setup my first test.

The following includes my test2.cir based on the given example at this link:

1- The schematic is available here. This file can be opened by gschem platform. Please notice to "netlist name, refdes, and value" parameters for each component.

2-now it is time to convert the schematic file to a netlist for spice simulator. We can easily do this by running "gnetlis" command of gEDA:
       [xx@localhost yy]$ gnetlist -g spice -o test2.cir test2.sch

3- run ngspice simulator:
        [xx@localhost yy]$ ngspice

4- source test2.cir
        ngspice 1 -> source test2.cir

5- for AC frequency analysis with linear scaling, step size of 1000Hz, over 0.1Hz-250KHz frequency band (more details are available here):
        ngspice 2 -> ac lin 1000 0.1 250KHz

6- there are two nodes indicated by n1 and n2 in the schematic. We can plot the voltage of these nodes over the above mentioned frequency range:
        ngspice 3 -> plot v(n2)