Processing math: 100%

Friday, September 15, 2017

op-amp with limited bandwidth



op-amp open loop transfer function: B(s)=Vo(s)Vx(s)=A1+swp, where wp is the first pole of op-amp and A is it's dc gain. Total charges at node x in sampling phase: qx=(C1+Cf)×Vi(s). Ideally, charges at node x cannot escape (no low impedance path exist); therefore, op-amp settles with respect to charge equilibrium at node x: qf+q1=qxCf(Vo(s)Vx(s))C1Vx(s)=(C1+Cf)×Vi(s) if β=CfC1+Cf, and given op-amp open loop transfer function (Eq. (2)): Vo(s)=B(s)1βB(s)Vi(s)H(s)=B(s)βB(s)1=A1+swp+βA=1β+1A11+swp(1+βA) where H(s) is the closed loop transfer function of the circuit. step response of H(s), Y(s) is given by: Y(s)=1β+1A(1s1s+wp(1+βA))y(t)=1β+1A(1ewp(1+βA)t) at the end of amplification period (t=Ts2), gain error is equal to: Gerr=1βy(t=Ts2)=1β1β+1A+1β+1Aewp(1+βA)2fs assumption 1- unity gain bandwidth of open loop op-am, fu, given A1: wu=wpA21Awpfu=Awp2π assumption 2- unity gain bandwidth of closed loop op-amp, fu given β+1Aβ: H(s)=1β2(1β+A)2+wuw2p=A2wu=Awp1β2fu=Awp1β22π for simplification, let's assume dc gain is relatively large; therefore, β+1Aβ: Gerr=1βeAβwp2fs for an N-bit pipeline, input refered gain error, Ginputerr=Gerr1β, should be better than quantization error: Ginputerr<2NAβwp2fs>Nln(2)fu>Nln(2)πβfs

Thursday, September 7, 2017

switch capacitor multiplier: op-amp with non-ideal DC gain



continue the discussion in previous post: here we assume a non-ideal op-amp, i.e. op-amp gain is equal A. For simplification, lets assume the circuit is in phase 2 and Vd=0 (similar to case b). Again, in equilibrium, sampling charge on C1 and Cf is conserved by the feedback loop (as much as DC gain of the op-amp allows). We have:

qfq1=Cf(VoVx)C1Vx=(C1+Cf)Vi.

If Vo=A×Vx then

VoCf+VoA(C1+Cf)=(C1+Cf)ViVo=C1+CfCf+C1+CfAVi=1β+1AVi,
where β=CfC1+Cf. If A then Vo=Viβ. Given Equation (27), The output voltage error, Voutputϵ due to non-ideal gain of op-amp is given by

Voutputϵ=(1β1β+1β)Vi=1β(11+1βA1)Vi=(Δ1+Δ)Vo,
where Δ=1βA. For simplification, we assume that βA1; therefore we have:

VoutputϵΔ×Vo


Saturday, September 2, 2017

switch capacitor multiplier: theory of operation

This note is helping me to understand the theory of operation in MDAC (e.g. pipeline ADCs).



phase 1) sampling: when S1t  is high, input voltage is sampled on C1 and Cf. For simplicity, let's assume C1=Cf=C. Total charge saved on C1 and Cf is q=2×C×Vi.

phase 2) amplification: when S2 is high and S1 is low, pre-charged C1 and Cf capacitors are placed in a feedback loop with an amplifier. let's review the following cases:

case (a) C1 left plat is floating and Cf is placed in the feedback loop.

case (a) C1 left plate is floating.

in this case, given C1=Cf=C, q=CVi. large gain of op-amp, would like to force Vx voltage to 0 volt through the feedback loop. If left plate of C1 is floating, C1's left plate potential settles at Vi and C1 continues holding q coulomb of charge. On the other hand, Vo must settle to Vi voltage to make sure that the rest of sampled charges are kept on Cf. The important point is that because node Vx is a high impedance node and left plate of C1 is also floating, op-amp output cannot inject any charge in the loop.

case (b) left plate of C1 capacitor is connected to ground. In this case, op-amp feedback loop pulls node Vx to zero volt.This means that C1 holds zero coulomb of charge. In addition, node Vx is a high impedance node; in equilibrium, the original q charge that was saved on C1 needs to be restored at node Vx. In other words, in equilibrium, Cf needs to store 2×q coulomb of charge, i.e. Vo=2×Vi. This is possible because op-amp can inject charge into the feedback loop at its output (low impedance node).

case (b) C1 left plate is ground.

case(c) left plate of C1 is connected to a voltage source Vd. Following the logic of case (b), in equilibrium, C1 stores q1=(VdVx)C1=VdC1 coulomb of charge. originally, C1 stored q=C1Vi coulomb of charge. The difference, between q and q1 should be stored on Cf (because node Vx is high impedance).  Consequently, in equilibrium,

Vo=q+q2Cf=2qq1Cf=C12ViVdCf=2ViVd.


case (c) C1 left plate is connected to Vd.
case (c) is a representation of MDAC (in this example 1 bit) with 2x amplification gain. Vo is the residual voltage that is transferred to the next pipeline stage.