Communications, Circuits and Systems: 2017

Wednesday, October 4, 2017

MDAC operation

according to [Pipeline ADC enhancement techniques; page 35], MDAC output voltage is given by:

$\begin{eqnarray} V_{out} &=& \frac{\Sigma_{1}^{2^n} c_i}{c_f} V_{in} - \left[ \frac{\Sigma_{1}^{k} c_i}{\Sigma_{1}^{2^n} c_i} V_{ref} -\frac{\Sigma_{k+1}^{2^n} c_i}{\Sigma_{1}^{2^n} c_i} V_{ref} \right] \end{eqnarray}$

question: is this equation accurate?

1- at sampling phase charge

$q=V_{in} \Sigma_{1}^{2^n} c_i$ is stored on sampling capacitors

$c_i$ ;

2- at amplification phase we have the superposition of the following cases:

case A) $c_i$ s' left plate is floating and op-amp settles to an equilibrium in which negative pin of op-amp is a virtual ground (all the charges that were stored are pulled to the left plate of $c_f$ by and electric field that is created by op-amp output voltage of the right plate of $c_f$ . In this case, to achieve equilibrium, $V_out$ should be

$\begin{eqnarray} V_{out} &=&\frac{\Sigma_{1}^{2^n} c_i}{c_f} V_{in} \end{eqnarray}$

case B) left plate of $c_i$ s are connected to either $V_{ref}$ or $-V_{ref}$ depending on sub-ADC output codes. Let's assume $k$ of sub-ADC codes are $1$ and the rest are $0$ . In this condition, we have average charge of $\Sigma_{1}^{k} c_i V_{ref} -\Sigma_{k+1}^{2^n} c_i V_{ref}$ that must be absorbed to to right plate of $c_i$ s in reciprocity with the electric field that is introduced by $\pm V_{ref}$ combinations. In addition, op-amp tends to holds the negative pin at virtual ground. Consequently, op-amp must create an opposite electric field to cancel the impact of input codes; The magnitude of this electric field (i.e. voltage at the right plate of $c_f$ ) should be enough to keep the balance of the charge at virtual ground, i.e.

$\begin{eqnarray} V_{out} &=&- 1 \times \frac{1}{c_f} \left[ \Sigma_{1}^{k} c_i -\Sigma_{k+1}^{2^n} c_i \right] V_{ref} \end{eqnarray}$

3- supposition of case A and B results in:

$\begin{eqnarray} V_{out} &=& \frac{\Sigma_{1}^{2^n} c_i}{c_f} V_{in} - \left[ \frac{\Sigma_{1}^{k} c_i - \Sigma_{k+1}^{2^n} c_i}{c_f} V_{ref }\right] \\ &=& \frac{\Sigma_{1}^{2^n} c_i}{c_f} \left[ V_{in} - \frac{\Sigma_{1}^{k} c_i - \Sigma_{k+1}^{2^n} c_i}{\Sigma_{1}^{2^n} c_i} V_{ref } \right] \end{eqnarray}$

Friday, September 15, 2017

op-amp with limited bandwidth

op-amp open loop transfer function:

$\begin{eqnarray} B \left( s \right) &=& \frac{V_o \left( s \right)}{V_x \left( s \right)} \\ &=& \frac{-A}{ 1+ \frac{s}{w_p} }, \label{eq:2} \end{eqnarray}$ where

$w_p$ is the first pole of op-amp and

$A$ is it's dc gain. Total charges at node

$x$ in sampling phase:

$-q_x = \left(C_1 + C_f \right) \times V_i \left( s \right)$ . Ideally, charges at node

$x$ cannot escape (no low impedance path exist); therefore, op-amp settles with respect to charge equilibrium at node

$x$ :

$\begin{eqnarray} -q_f + q_1 &=& -q_x \\ C_f \left( V_o \left( s \right) - V_x \left( s \right) \right) - C_1 V_x \left( s \right) &=& \left(C_1 + C_f \right) \times V_i \left( s \right) \\ \end{eqnarray}$ if

$\beta = \frac{C_f}{C_1 + C_f}$ , and given op-amp open loop transfer function (Eq.

$\eqref{eq:2}$ ):

$\begin{eqnarray} V_o \left( s \right) &=& \frac{-B \left( s \right) }{1- \beta B \left( s \right)} V_i \left( s \right)\\ H \left( s \right) &=& \frac{B \left( s \right) }{\beta B \left( s \right) -1} \\ &=& \frac{A}{1+\frac{s}{w_p}+\beta A} \\ &=& \frac{1}{\beta + \frac{1}{A}} \frac{1}{1+\frac{s}{w_p \left( 1+\beta A \right)}} \end{eqnarray}$ where

$H\left( s \right)$ is the closed loop transfer function of the circuit. step response of

$H\left(s \right)$ ,

$Y\left(s\right)$ is given by:

$\begin{eqnarray} Y\left(s\right) &=& \frac{1}{\beta + \frac{1}{A}} \left( \frac{1}{s} -\frac{1}{s+w_p\left(1+\beta A\right)} \right) \\ y\left( t \right) &=& \frac{1}{\beta + \frac{1}{A}} \left(1-e^{-w_p\left(1+\beta A\right) t} \right) \end{eqnarray}$ at the end of amplification period (

$t=\frac{T_s}{2}$ ), gain error is equal to:

$\begin{eqnarray} G_{\text{err}} &=& \frac{1}{\beta} - y\left( t=\frac{T_s}{2} \right) \\ &=& \frac{1}{\beta} - \frac{1}{\beta+\frac{1}{A}} + \frac{1}{\beta+\frac{1}{A}} e^{\frac{-w_p\left( 1+\beta A \right)}{2 f_s}} \end{eqnarray}$ assumption 1- unity gain bandwidth of open loop op-am,

$f_u$ , given

$A \gg 1$ :

$\begin{eqnarray} w_u &=& w_p \sqrt{A^2-1} \\ &\approx& A w_p \\ f_u &=& \frac{A w_p}{2 \pi} \label{eq:15} \end{eqnarray}$ assumption 2- unity gain bandwidth of closed loop op-amp,

$f_u^{*}$ given

$\beta + \frac{1}{A} \approx \beta$ :

$\begin{eqnarray} H\left( s \right) &=& 1 \\ \beta^2 \left( \frac{1}{\beta} + A \right)^2 + \frac{w_u^{*}}{w_p^2} &=& A^2 \\ w_u^{*} &=& A w_p \sqrt{1-\beta^2} \\ f_u^{*} &=& \frac{A w_p \sqrt{1-\beta^2}}{2 \pi} \end{eqnarray}$ for simplification, let's assume dc gain is relatively large; therefore,

$\beta + \frac{1}{A} \approx \beta$ :

$\begin{eqnarray} G_{\text{err}} &=& \frac{1}{\beta} e^{\frac{-A \beta w_p}{2 f_s}} \end{eqnarray}$ for an

$N$ -bit pipeline, input refered gain error,

$G_{\text{err}}^{\text{input}} = \frac{G_{\text{err}}}{\frac{1}{\beta}}$ , should be better than quantization error:

$\begin{eqnarray} G_{\text{err}}^{\text{input}} &<& 2^{-N} \\ \frac{A \beta w_p}{2 f_s} &>& N \ln \left(2\right) \\ f_u &>& \frac{N \ln \left(2\right) }{\pi \beta} f_s \end{eqnarray}$

Thursday, September 7, 2017

switch capacitor multiplier: op-amp with non-ideal DC gain

continue the discussion in previous post: here we assume a non-ideal op-amp, i.e. op-amp gain is equal

$A \neq \infty$ . For simplification, lets assume the circuit is in phase 2 and

$V_d=0$ (similar to case b). Again, in equilibrium, sampling charge on

$C_1$ and

$C_f$ is conserved by the feedback loop (as much as DC gain of the op-amp allows). We have:

$\begin{eqnarray} q_f-q_1 &=& C_f\left(V_o-V_x \right) - C_1 V_x \nonumber \\ &=& \left( C_1+C_f \right) V_i. \end{eqnarray}$

If

$V_o=-A \times V_x$ then

$\begin{eqnarray} V_o C_f + \frac{V_o}{A} \left(C_1+C_f\right) &=& \left(C_1+C_f \right) V_i \\ V_o &=& \frac{C_1+C_f}{C_f+\frac{C_1+C_f}{A}} V_i \\ &=& \frac{1}{\beta+\frac{1}{A}} V_i, \label{eq:3} \end{eqnarray}$
where

$\beta=\frac{C_f}{C_1+C_f}$ . If

$A \rightarrow \infty$ then

$V_o^{*} = \frac{V_i}{\beta}$ . Given Equation

$\eqref{eq:3}$ , The output voltage error,

$V_{\epsilon}^{\text{output}}$ due to non-ideal gain of op-amp is given by

$\begin{eqnarray} V_{\epsilon}^{\text{output}} &=& \left( \frac{1}{\beta} - \frac{1}{\beta+\frac{1}{\beta}} \right) V_i \\ &=& \frac{1}{\beta} \left( \frac{1}{1+\frac{1}{\beta A}} -1 \right) V_i &=& \left( \frac{\Delta}{1+\Delta} \right) V_o^{*}, \end{eqnarray}$
where

$\Delta=\frac{1}{\beta A}$ . For simplification, we assume that

$\beta A \gg 1$ ; therefore we have:

$\begin{eqnarray} V_{\epsilon}^{\text{output}} &\cong& \Delta \times V_o^{*} \end{eqnarray}$

Saturday, September 2, 2017

switch capacitor multiplier: theory of operation

This note is helping me to understand the theory of operation in MDAC (e.g. pipeline ADCs).

phase 1) sampling: when

$S_{1t}$ is high, input voltage is sampled on

$C_1$ and

$C_f$ . For simplicity, let's assume

$C_1 = C_f = C$ . Total charge saved on

$C_1$ and

$C_f$ is

$q=2 \times C \times V_i$ .

phase 2) amplification: when

$S_2$ is high and

$S_1$ is low, pre-charged

$C_1$ and

$C_f$ capacitors are placed in a feedback loop with an amplifier. let's review the following cases:

case (a)

$C_1$ left plat is floating and

$C_f$ is placed in the feedback loop.

case (a)

$C_1$ left plate is floating.

in this case, given

$C_1 = C_f = C$ ,

$q=C V_i$ . large gain of op-amp, would like to force

$V_x$ voltage to

$0$ volt through the feedback loop. If left plate of

$C_1$ is floating,

$C_1$ 's left plate potential settles at

$V_i$ and

$C_1$ continues holding

$q$ coulomb of charge. On the other hand,

$V_o$ must settle to

$V_i$ voltage to make sure that the rest of sampled charges are kept on

$C_f$ . The important point is that because node

$V_x$ is a high impedance node and left plate of

$C_1$ is also floating, op-amp output cannot inject any charge in the loop.

case (b) left plate of

$C_1$ capacitor is connected to ground. In this case, op-amp feedback loop pulls node

$V_x$ to zero volt.This means that

$C_1$ holds zero coulomb of charge. In addition, node

$V_x$ is a high impedance node; in equilibrium, the original

$q$ charge that was saved on

$C_1$ needs to be restored at node

$V_x$ . In other words, in equilibrium,

$C_f$ needs to store

$2\times q$ coulomb of charge, i.e.

$V_o=2\times V_i$ . This is possible because op-amp can inject charge into the feedback loop at its output (low impedance node).

case (b)

$C_1$ left plate is ground.

case(c) left plate of

$C_1$ is connected to a voltage source

$V_d$ . Following the logic of case (b), in equilibrium,

$C_1$ stores

$q_1 = \left(V_d-V_x \right)C_1 = V_d C_1$ coulomb of charge. originally,

$C_1$ stored

$q = C_1 V_i$ coulomb of charge. The difference, between

$q$ and

$q_1$ should be stored on

$C_f$ (because node

$V_x$ is high impedance). Consequently, in equilibrium,

$V_o = \frac{q+q_2}{C_f} = \frac{2q-q_1}{C_f} = C_1 \frac{2V_i-V_d}{C_f} = 2V_i-V_d$ .

case (c)

$C_1$ left plate is connected to

$V_d$ .

case (c) is a representation of MDAC (in this example 1 bit) with 2x amplification gain.

$V_o$ is the residual voltage that is transferred to the next pipeline stage.

Monday, July 24, 2017

setup and hold characterization

find the meta stability point by sweeping data vs. clock. metal stability region can be identify by clk-to-Q propagation delay measurements. this link includes references to more formal definition.