NGSPICE / gEDA startup

I have installed ngspice simulator and gEDA products over a CentOS5.8 virtual machine. I had problems installing it over debian and FreeBSD but CentOS is good so far.

I can draw the schematic of the circuits in gschem (schematic drawer of gEDA) and make a netlist from the given schem for importing into ngspice. The only trick is to assign reasonable netlist name, refdes, and value to each component in the schematic.  Here is a good tutorial that helped me to setup my first test.

The following includes my test2.cir based on the given example at this link:

1- The schematic is available here. This file can be opened by gschem platform. Please notice to "netlist name, refdes, and value" parameters for each component.

2-now it is time to convert the schematic file to a netlist for spice simulator. We can easily do this by running "gnetlis" command of gEDA:
       [xx@localhost yy]$ gnetlist -g spice -o test2.cir test2.sch

3- run ngspice simulator:
        [xx@localhost yy]$ ngspice

4- source test2.cir
        ngspice 1 -> source test2.cir

5- for AC frequency analysis with linear scaling, step size of 1000Hz, over 0.1Hz-250KHz frequency band (more details are available here):
        ngspice 2 -> ac lin 1000 0.1 250KHz

6- there are two nodes indicated by n1 and n2 in the schematic. We can plot the voltage of these nodes over the above mentioned frequency range:
        ngspice 3 -> plot v(n2)

Circuit vs. Device level Simulator

Here is a nice review comparing a circuit level simulator, (e.g. NGSPICE), versus a device simulator, (e.g. General purpose Semiconductor Simulator). It also describes how users can integrate GSS in NGSPICE. I would like to share the following figure from the document that clarifies the difference from a high-level perspective.

  

3PGCIC presentation

The presentation slides are available here. The full paper can be find at this link.

Frequency Dividers

"Frequency Divider Design for Mlti-GHz PLL Systems" is the title of a dissertation by "Francesco Barale" that sufficiently reviews various frequency dividers used in a PLL loop. The dissertation compares programmable divider (a digital counter) with analog divider solutions (master-slave latch divider, MS divider, and injection-locking divider, ILD). It concludes that for multi-GHz PLLs, analog dividers should be used in the first stages of the clock dividing branch, as show below:

Fig. 6 on page 11: It is recommended that ILD comes at the very first stage ("The ILD solution allows the highest frequency of operation but, in general, offers a narrower bandwidth and higher power consumption when compared with the MS solution").